This disclosure relates to reducing the number of sequential operations such as atomic operations to be performed on a shared memory cell.
Parallel processing can be implemented in a computer system to achieve faster execution of applications over traditional sequential processing. For example, a single instruction multiple data (SIMD) instruction is an example parallel process where a single instruction is performed simultaneously on multiple data. Such SIMD instructions can help speed up data processing in applications including multimedia, video, audio encoding/decoding, 3-Dimensional (3-D) graphics and image processing.
However, in a computer system that supports parallel processing, certain program operations that access a same memory cell in the computing system may need to be synchronized to ensure against unintended results such as data corruption if the program operations access the same memory cell in parallel. For example, program operations may need to be synchronized because the result to be stored in a memory cell of one program operation may be needed to perform another program operation.
Synchronization of program operations that access the same memory cell can be achieved by placing these program operations in a critical section. In a critical section, operations are performed sequentially, for example using atomic operations, instead of concurrently in parallel to ensure that the shared memory cell is accessed serially by the program operations thereby avoiding data corruption or other unintended results.
Generally, an atomic operation may be one or more computer operation(s) (e.g., read, modify, and then write to a memory cell) that a computing system forces to be completed (e.g., using a lock variable) prior to execution of a subsequent computer operation. Thus, by placing program operations that access a same memory cell in a critical section, the shared memory cell is accessed serially by the program operations thereby avoiding data corruption or other unintended requests.
The synchronization of program operations that access the same memory cell, however, may reduce the efficiency of parallel processing architectures.